Arrangement for transmitting data over a bus

ABSTRACT

An arrangement for transmitting data over a bus (2, 6, 7) has a central unit (1, 4, 5) which initiates data transmission and one or several peripheral units (3, 8, 9) linked to each other by the bus. In at least one of the components, besides first control lines and data lines for transmitting a data word having a first data width, further control lines and further data lines for transmitting a data word having a second data width are also provided. These are designed in such a way that components with different data bus widths can communicate with each other by transmission of data words having the smallest existent data width. In automation equipment, the invention allows any combination of components of different classes of capacity.

BACKGROUND OF THE INVENTION

The present invention concerns an arrangement for transmitting data overa bus having a central unit which initiates data transmission and one orseveral peripheral units linked to each other by the bus.

An arrangement of this sort is known from the DE-PS 31 33 407. There, aprocessor as a central unit is connected to a memory as a peripheralunit by a bus. The bus contains data lines whose number corresponds tothe word width, address lines for addressing the individual memory cellsand control lines for controlling the data transmission. Datatransmission can take place selectably as 8-bit-wide byte accesses or16-bit-wide word accesses. To select the access mode, besides READ andWRITE signals, a BYTE signal is also provided which is evaluated in acontrol signal decoder. The processor executes a fixed microprogramwhich is tailored to the special hardware configuration. A change in thenumber of data lines thus leads necessarily to a change in themicroprogram. For example, the memory cannot be easily replaced by amemory of another data width.

In electronic, modularly designed devices in which the componentscentral unit, peripheral unit and bus are interchangeable, there existboth cost-effective devices with a small data bus width as well asdevices of the upper class of capacity which are characterized by a databus of large width.

The underlying object of the invention is to create an arrangement inwhich the components of different classes of capacity can be combinedtogether in any way.

SUMMARY OF THE INVENTION

The present invention achieves this objective by providing anarrangement for transmitting data over a bus having a central untilwhich initiates data transmission and one or more peripheral unitslinked to each other by the bus, the units and the bus having firstcontrol lines for a first transmission request signal of the centralunit and for a first transmission acknowledgement signal of a peripheralunit for parallel transmission of a data word of a first data width andat least one unit and/or the bus having second control lines forparallel transmission of a data word of a second data width, which carrya second transmission request signal and a second transmissionacknowledgement signal, such that the second transmission request signalin the peripheral unit and the second transmission acknowledgementsignal in the central unit assume an active state only if all devicesinvolved in the transmission have second control lines.

In the arrangement the second data width can be a multiple of the first.In fact, there can be three different data widths achievable, 8 bits, 16bits and 32 bits. The units can be plug-in modules while the bus canconstitute a rear panel wiring of a card rack. The arrangement caninclude a further control line to indicate bus usage which is activatedduring transmission of the data word of the second data width if not alldevices involved in the transmission have second control lines such thatthe data word of a second data width is transmitted through transmissionof a number corresponding to the multiple of successive data words ofthe first data width.

The invention has the advantage that components of different classes ofcapacity can be combined together in a modular device. To connect acentral unit or peripheral units to the bus, which can be designed asrear-panel wiring in a card rack, no particular card slots suitable onlyfor modules of specific classes of capacity are required. The modules ofdifferent classes of capacity can be arranged according to the inventionin any given slot. For example, the operation of modules having a 32-bitdata bus width is possible in a card rack having an 8-bit data bus widthin the rear-panel wiring. The invention allows in this manner a gradualincrease in capacity from 8-bit to 32-bit data bus width by exchangingindividual components as part of a quasi-flowing transition withouthaving to exchange the entire device in one step. The arrangementaccording to the invention allows the use of future, powerful componentsin today's card rack, while at the same time components in common usetoday can be used in a future card rack. No additional circuit-relatedcost arises for components of the lower class of capacity due to thisfreedom.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be explained with reference to the drawings.

FIG. 1 shows an exemplary embodiment of the present invention.

FIG. 2 shows the signal coding associated with the present invention intabular form.

DETAILED DESCRIPTION

According to FIG. 1, a modular device has a central unit 1, a bus 2 anda peripheral unit 3, each of which has a 32-bit-wide data bus. The rangeof capacity of the central unit 1 includes that of a central unit 4having a 16-bit-wide data bus, which in turns encompasses that of acentral unit 5 having an 8-bit-wide data bus. The same appliesanalogously to the bus 2 and a 16-bit-wide bus 6 as well as an8-bit-wide bus 7 and to the peripheral unit 3, a peripheral unit 8having a 16-bit-wide data bus connection and a peripheral unit 9 havingan 8-bit data bus. All of these components which are involved in theexchange of data can be combined in any manner. In the simplest case,the central unit 5, the bus 7 and the peripheral unit 9 are used, eachof which has available an 8-bit-wide data bus connection. In thisminimum configuration, connecting elements 10 and 11 for thetransmission of data signals D0 . . . D7, connecting elements 12 and 13for the transmission of control signals RD (READ), WR (WRITE) and BL(BUS LOCK) as well as connecting elements 14 and 15 for the transmissionof a control signal R8 (READY 8 BIT) as an acknowledgement signal for8-bit data transmission are present. There is no need to examine ingreater detail the sequence in time of data transmission since it iscommon knowledge to those skilled in the art.

In a modular device of the middle class of capacity having a 16-bit-widedata bus connection in each of the central unit 4, the bus 6 and theperipheral unit 8, connecting elements 16 and 17 for the transmission ofdata signals D8 . . . D15, connecting elements 18 and 19 for thetransmission of a control signal WS (WORD SELECT) that designates 16-bitword accesses as well as connecting elements 20 and 21 for thetransmission of a control signal R16 (READY 16 BIT), which is used as anacknowledgement signal for 16-bit data transmission, are added. For themaximum configuration having a 32-bit data bus in each of the centralunit 1, the bus 2 and the peripheral unit 3, these are extended toinclude connecting elements 22 and 23 for the transmission of datasignals D16 . . . D31, connecting elements 24 and 25 for thetransmission of a control signal DWS (DOUBLE WORD SELECT) with which a32-bit double word access can be selected and connecting elements 26 and27 for the transmission of a control signal R32 (READY 32 BIT) as anacknowledgement signal for 32-bit data transmission. The address signalsA0 . . . A17 required for addressing are omitted in FIG. 1 for the sakeof clarity. In the maximum configuration, read and write accesses can beperformed in a double-word, word and also byte manner, i.e., with a32-bit, 16-bit or 8-bit data width. If, however, one of the components -central unit, bus or peripheral unit - has a lesser data bus width, thisrestricts the data width of the accesses. The conversion, for example,of a 32-bit access of the central unit 1 into suitable 8-bit or 16-bitaccesses is handled by a bus interface which is integrated into thecentral unit 1. Thus, cost-effective plug-in modules having an 8-bitdata bus connection can be used as peripheral units. Based on thecontrol signals, the bus interface then handles all write and readaccesses on the bus generally in the form of byte accesses.

The present invention is usable as such even in more complex automationequipment in which the central unit 1 is located in a central card rackand the peripheral unit 3 in an extended card rack. The bus 2 is thenimplemented by an interface module of the two card racks, and theconnecting elements between the individual components correspond to therear-panel wirings of the individual card racks.

Based on the table in FIG. 2, the coding of the individual controlsignals and the sequence of data transmission is explained hereafter. Inthe left column group separated by thick lines, the access request ZW,the address signals A1 and A0 and the control signals WS (WORD SELECT)and DWS (DOUBLE WORD SELECT) are listed. The right column group containsin each case for peripheral units PE having a 32-bit, 16-bit or 8-bitdata width an indication of the used data lines DA, the state of theacknowledgement signals R8, R16 and R32 as well as the implementedaccess mode ZA. The rows of the table contain in each case the states ofthe signals for a specific access request ZW. The L indicatorcorresponds to a Low state on a signal line, and the H indicator to aHigh state. For the address signals A1 and A0, the Low state implies theoutput of the value "0"; for the control signals WS, DWS, R8, R16 andR32, it represents the active state.

A double word access by the central unit ZE to an even word address(A0=L, A1=L) corresponding to the first row of the table is indicated bythe signal states WS=L and DWS=L. These signal states appear in theperipheral unit PE only if the signals on the entire signal path up tothe peripheral unit PE do not "become lost" somewhere. This is the caseonly if all components have available a 32-bit data bus connection. Aperipheral unit having a 32-bit data bus receives under this conditionthe signal states uncorrupted, acknowledges with a low state L of theacknowledgement signal R32 and transmits with the data signals D0 . . .D31 in the double word access mode DW. Transmission of the double wordis thus completed. If, on the other hand, the double word access requestDW of the central unit ZE is directed to a peripheral unit PE having a16-bit data bus connection which peripheral unit PE has no connectionfor the control signal DWS, then it receives only the low state L of thecontrol signal WS. For this peripheral unit PE, the double word accessrequest DW is equivalent to a word access request W. Therefore, itacknowledges this access request with a low state L of theacknowledgement signal R16 and executes the access with the data signalsD0 . . . D15 in the access mode W. The bus interface of the central unitZE which bus interface detects the word access through the Low state ofthe acknowledgement signal R16 executes, in order to complete the doubleword access, a further word access at the next higher address which wordaccess is characterized by the signal states in the seventh row of thetable. In this process, the signal BL (BUS LOCK), not shown in thetable, can be set to the active state in order to ensure successivetransmission of the two data words. After transmission of the completedouble word has occurred, the signal BL is reset to its previous state.

A peripheral unit PE having an 8-bit data connection receives neitherthe control signal WS nor the control signal DWS. It interprets a doubleword access request DW as a byte access B, acknowledges with a Low stateof the control signal R8 and performs the transmission of the byte onthe data lines D0 . . . D7. The bus interface in the central unit ZErecognizes through the acknowledgement signal R8 the byte access whichoccurred and performs thereupon for an active signal BL the remainingthree byte accesses of the double word transmission at respectiveincremented addresses. The codings of the states for these threeaccesses can be taken from rows 10, 11 and 12 of the table. These byteaccesses are identical to those of a central unit having an 8-bit databus connection. From the viewpoint of the peripheral unit having an8-bit data bus width, there is thus no noticeable difference between thedifferent central units. Naturally, the central unit ZE having a 32-bitdata bus connection can also output a word or byte access request forwhich the signal states in rows 5, 7 and 9 . . . 12 of the table areindicated. The access requests marked with a "*" are not provided in theexemplary embodiment. A "-" as the signal state of the acknowledgementsignals R16 or R32 in the table means that no state is generated forthis signal by the corresponding unit such that the central unit ZEalways receives a High state for this signal which High state isguaranteed by wiring the signal line with a PULL-UP resistor.

If the signal paths to a peripheral unit having a 32-bit data busconnection are connected only with a 16-bit or 8-bit data bus width, itreacts to double word and word accesses like a peripheral unit having a16-bit or 8-bit data bus connection. Likewise, a peripheral unit havinga 16-bit data bus connection reacts to double word and word accesseslike a peripheral unit having an 8-bit data bus connection for an 8-bitdata bus width.

Double word access requests of a central unit having an 8-bit data busconnection are always implemented as four successive byte accesses viathe data signals D0 . . . D7 with an activated control signal BL.Analogously, double word accesses of a central unit having a 16-bit dataconnection take place as two successive word accesses.

If a double word access has to be performed at an uneven word address(A0=H or A1=H), even central units having a 32-bit data bus connectionbreak up this access into multiple successive bus operations with anactivated control signal BL.

What is claimed is:
 1. An arrangement for transmitting data over a bussaid arrangement having a central unit which initiates data transmissionand one or more peripheral units linked to each other by the bus, theunits and the bus having first control lines for a first transmissionrequest signal of the central unit and for a first transmissionacknowledgement signal of a peripheral unit for parallel transmission ofa data word of a first data width, at least one unit and/or the bushaving second control lines for parallel transmission of a data word ofa second data width, which carry a second transmission request signal inthe peripheral unit and a second transmission acknowledgement signal inthe central unit, such that the second transmission request signal inthe peripheral unit and the second transmission acknowledgement signalin the central unit assume an active state only if all devices involvedin the transmission have second control lines.
 2. The arrangementaccording to claim 1, wherein the second data width is a multiple of thefirst data width.
 3. The arrangement according to claim 2, wherein theunits and the bus have a further control line to indicate bus usagewhich is activated during transmission of a data word of the second datawidth if not all devices involved in the transmission have secondcontrol lines such that the data word of the second data width istransmitted as a number of data words of the first data width, whereinthe number of data words of the first data width corresponds to themultiple by which the second data width exceeds the first data width. 4.The arrangement of claim 1, further comprising additional control linesfor parallel transmission of data words corresponding to at least onefurther data width.
 5. The arrangement of claim 4, wherein the firstdata width is equal to 8 bits, the second data width is equal to 16 bitsand a further data width is equal to 32 bits.
 6. The arrangement ofclaim 1, wherein the units are plug-in modules and the bus comprises arear-panel wiring of a card rack.
 7. The arrangement of claim 1, whereinthe arrangement is a part of automation equipment.
 8. A central unit,peripheral unit or bus for use in an arrangement according to claim 1,wherein the arrangement has control lines for parallel transmission of adata word of the second data width.